The present invention relates to packet-oriented transfers of data and other information in a computer network. More particularly, the present invention relates to a method and apparatus for staging data in elements of a staging memory and for transferring data between a device interface and the elements of a staging memory via a direct memory access (DMA) channel.
Packet switching is a known system for transmitting information such as data, commands and responses over a shared bus of a computer system or network by placing the information in packets having a specified format and transmitting each packet as a composite whole. Long transmissions, such as transfers of large amounts of data, are broken up into separate packets to reduce the amount of time that the shared bus is continuously occupied by a single transmission. Each packet typically includes a header of control elements, such as address bits and packet identification bits arranged in predetermined fields, and may further include error control information.
One known packet-switching method, described in Strecker et al. U.S. Pat. No. 4,777,595, requires that all packet transmissions occur between a named buffer in a transmitting node and a named buffer in a receiving node. The named buffers are in actual memory at each node. To write data from one node to another, the data is placed in packets each labeled in designated fields with the name of the destination buffer in the receiving node and an offset value. The offset value of the packet specifies the location in the receiving buffer, relative to the starting address of the buffer, where the first byte of data in that particular packet is to be stored. A transaction identifier unique to the group of packets also is transmitted in a separate field of each packet. The transaction identifier is used in the process of confirming transmission of the packets.
This packet-switching method has considerable drawbacks in that it requires a node to have a named destination buffer in actual memory for receiving packet transmissions, and further requires that the receiving node identify its named destination buffer to the transmitting node prior to a data transfer. It also has the drawback of requiring that the receiving node be responsive to the contents of the destination buffer name field of a transmitted data packet for directing the contents of the packet to the named buffer. These drawbacks are particularly evident if one attempts to impose them on a receiving node which comprises a resource shared by multiple computers in a network.
For example, consider a mass storage system acting as a shared resource for several computers in a computer network. The mass storage system must often process data transfer requests from more than one computer concurrently, and the data involved in each of these transfers is often sufficiently large to require that it be divided among several packets for transmission over the network communication bus. Depending on the protocol of the communication bus and the relative priorities of the transfers, the mass storage system may receive packets associated with one data transfer between packets associated with another transfer.
Typically, the mass storage system has a memory through which data passes in transit between a network communication bus device interface and a mass storage device interface. This memory may also handle packets having control messages directed between a system processor of the mass storage system and other processors (e.g., remote processors on the network bus or other processors in the mass storage system). The packets containing data or control messages are transferred between the memory and the device interface by one or more DMA channels. Such a DMA channel comprises a high-speed communications interface, including a data bus and control circuitry, for transferring data directly into or out of memory without requiring the attention of a system processor after initial set-up.
If the mass storage system, prior to receiving a data transmission from any one of the computers in the network, were required to allocate a named buffer space in memory to accept the entire data transfer (which may be many packets long), the concurrent processing of several such data transfer requests would require that the mass storage system concurrently allocate a number of separate named buffer spaces equal to the number of concurrent transfers being processed. This preallocation of separate named buffers in the memory of the mass storage system ties up the memory, resulting in inefficient use of available memory and possibly limiting the data throughput of the mass storage system by restricting the number of data requests that can be processed concurrently.
Greater efficiency (in terms of memory use) can be achieved by a more dynamic allocation of memory on a packet-by-packet basis, such that memory space for a particular incoming expected packet is not allocated until the packet is received by the mass storage system. Moreover, efficiency is improved by allowing packets to be stored at any available location in the memory. Such arbitrary, packet-by-packet allocation of memory is particularly suited to the memory of a mass storage system. Unlike transfers of data between actual memory of one computer and actual memory of another computer, transfers of data involving a mass storage system do not use the memory of the mass storage system as a final destination for the data. Rather, as described above, packets containing data are only passed through the memory in transit between the communication bus of the network and the mass storage device or devices of the system. Data comes and goes through the memory in two directions (i.e., into and out of mass storage) arbitrarily, depending on the demands of the computers in the network and the conditions (e.g., busy or idle) of the communication bus, the mass storage devices and the data channels leading to the mass storage devices. As a consequence, the amount and specific locations of memory space used at any particular time, and conversely the amount and specific locations available to receive packets, continually varies. Particular memory locations arbitrarily cycle between available and unavailable states. In such circumstances, preallocation of named buffer spaces in memory is clearly and unnecessarily inefficient.
In view of the foregoing, it would be desirable instead to permit packets to be placed arbitrarily in available memory locations without regard to their source, contents or relationship to other packets--thus allowing the mass storage system to allocate memory locations based on immediate need and immediate availability (i.e., the memory is free to place an incoming packet in whatever memory location happens to be available when the packet is received by the system). Likewise it would be desirable to permit data from the mass storage devices to be transferred to arbitrary locations in the memory in preparation for transmission over the network communication bus--again allowing the mass storage system to allocate memory locations based on immediate need and immediate availability. Of course, it would further be desirable to be able to retrieve data from arbitrary places in memory and to assemble the data in logical order either for transfer to mass storage or for transmission over the network communication bus.
Packet-switching networks are known in the art that do not require a receiving node to identify a named destination buffer prior to transferring a packet from memory to memory. These networks use various methods for directing the contents of packets into the receiving memory such as, for example, by maintaining a software-controlled address table in the memory of the receiving node, the entries of which are used to point to allocated memory locations unknown to the transmitting node. The present invention adopts the principle of such networks in that it is an object of the present invention to provide a method and apparatus for transferring packets between a network communication bus and memory, without allocating or identifying named buffers.
However, known computer systems typically transfer data into and out of contiguous locations in memory to minimize processor interrupts and simplify the transfer process. In known computer systems in which data is stored in disjoint memory locations, a separate processor interrupt is usually required to transfer each non-contiguous segment of data into and out of memory. The present invention is an improvement over such systems in that with respect to the writing of data from memory to a device interface, non-contiguous segments of data stored in the memory are joined by DMA control logic to form a contiguous DMA data transfer to the device interface, and in that, with respect to the reading of data into memory from the device interface, a contiguous DMA data transfer from the device interface is routed by DMA control logic into selected not necessarily contiguous segments of memory in the staging memory. After initial set-up processor attention is not required in either case to transfer the individual data segments until the entire transfer is completed.